RAMON.space is named in memory of
Colonel Ilan Ramon, Israeli astronaut
who died on board the Columbia space shuttle
February 1st, 2003
RAMON.space also remembers Col. Ilan Ramon's son, Assaf Ramon, and wife, Rona Ramon.
Assaf died in an Air Force fighter plane crash in 2009. Rona tragically joined her late husband and son in 2018. Rona encouraged and supported Ramon Chips. She devoted her life to Mankind, and called upon us to volunteer and contribute to space education of young generations and to partake in promoting excellence and leadership in school students. Ramon.Space is committed to continue supporting Rona's initiatives.
Ramon.Space will cherish their memory forever.
Ran Ginosar, PhD (CEO), Professor of Electrical Engineering, Technion—Israel Institute of Technology and Head, VLSI Systems Research Center at Technion. BSc (Technion), PhD (Princeton). Expert in VLSI architectures, many-cores, and rad-hard ASIC design.
Dov Alon (VP Engineering), BSc and MSc EE (Technion). Was VLSI Design Center Manager at Rafael–Israel Armament Development Authority, responsible for developing 80 ICs for communication and DSP applications. Was President and CEO of IC4IC Inc, a privately held fabless semiconductor company in the 3G wireless infrastructure market. Expert on rad-hard ASIC design.
Tuvia Liran (CTO), BSc and MSc, Physics and EE (Technion). Was product engineering manager, responsible for productization of several high end MPUs at National Semiconductor’s fab in Israel, and managed VLSI design at iSight, a video processor company. Consulted to several companies in Israel on design for manufacturability, analog/mixed-signal design and back-end design methodologies. Expert on rad-hard circuits and physical ASIC / VLSI design.
Fredy Lange (VP R&D), BSc EE (Technion) and MBA (Tel-Aviv). Was Silicon Design manager at Texas Instruments, Analog Devices and National Semiconductors, responsible for developing successful generations of connectivity mixed-signal products (BT, WLAN, GPS, NFC), TigerSHARC DSP, audio sigma-delta codecs, Super I/O and embedded voice/fax products. Expert in circuits, chip design and verification, and in assembling and leading chip design organizations.
Peleg Aviely (Sr. Architect), BSc EE (Ben Gurion). Was CTO and VP R&D of Plurality LTD, a fabless semiconductor company that developed many-core architecture for on-chip parallel computing. Expert on development of parallel embedded system platforms and their parallel programming model.
David Goldfeld (Director of Software), BA and MA Computer Sciences (Technion). Was at Intel, SW Manager Director and Site Manager in SSG, EZchip Director SW department manager, GM of PID which became Intergraph development center. Vast experience with leading versatile SW development teams, mostly in HW-SW co-design, among them in domains of CPU and system Simulation, Networking, Cyber and Engineering Asset management.
Roy Nesher (Director of VLSI), BSc EE (Technion) and MBA (Kellog-Recanati). Was R&D manager at TranSwitch responsible for delivering successful ASIC and IPs for high speed mixed signals interfaces (HDMI, DisplayPort, 10/100/1G Ethernet Phy) for consumer electronic and communication markets, Director of VLSI and Software at Ceragon Networks and VLSI leader at PMC-Sierra and Intel. Expert in management of VLSI design teams, ASIC projects and R&D.
Dror Reznik (Director of Verification and Validation), BSc EE (HIT). Was design verification engineer at Metalink, DV and CAD lead at Siverge-Network, DV team leader at Veriest-V, Cisco Systems, Synopsys and Qualcomm. Extensive experience in VLSI pre- and post-silicon verification, in ramping and managing design verification teams, constraint driven functional verification environments, RTL simulations and CAD.